//===- IntrinsicsRISCV.td - Defines RISCV intrinsics -------*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file defines all of the RISCV-specific intrinsics. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Atomics // Atomic Intrinsics have multiple versions for different access widths, which // all follow one of the following signatures (depending on how many arguments // they require). We carefully instantiate only specific versions of these for // specific integer widths, rather than using `llvm_anyint_ty`. // // In fact, as these intrinsics take `llvm_anyptr_ty`, the given names are the // canonical names, and the intrinsics used in the code will have a name // suffixed with the pointer type they are specialised for (denoted `
` in the
// names below), in order to avoid type conflicts.
let TargetPrefix = "riscv" in {
// T @llvm. (any*, T, T, T imm);
class MaskedAtomicRMWFourArg (any*, T, T, T, T imm);
class MaskedAtomicRMWFiveArg (any*, i32, i32, i32 imm);
def _i32 : MaskedAtomicRMWFourArg (any*, i64, i64, i64 imm);
def _i64 : MaskedAtomicRMWFourArg (any*, i32, i32, i32, i32 imm);
def _i32 : MaskedAtomicRMWFiveArg (any*, i64, i64, i64, i64 imm);
def _i64 : MaskedAtomicRMWFiveArg (...)
defm int_riscv_masked_atomicrmw_xchg : MaskedAtomicRMWFourArgIntrinsics;
defm int_riscv_masked_atomicrmw_add : MaskedAtomicRMWFourArgIntrinsics;
defm int_riscv_masked_atomicrmw_sub : MaskedAtomicRMWFourArgIntrinsics;
defm int_riscv_masked_atomicrmw_nand : MaskedAtomicRMWFourArgIntrinsics;
// Signed min and max need an extra operand to do sign extension with.
defm int_riscv_masked_atomicrmw_max : MaskedAtomicRMWFiveArgIntrinsics;
defm int_riscv_masked_atomicrmw_min : MaskedAtomicRMWFiveArgIntrinsics;
// Unsigned min and max don't need the extra operand.
defm int_riscv_masked_atomicrmw_umax : MaskedAtomicRMWFourArgIntrinsics;
defm int_riscv_masked_atomicrmw_umin : MaskedAtomicRMWFourArgIntrinsics;
// @llvm.riscv.masked.cmpxchg.{i32,i64}. (...)
defm int_riscv_masked_cmpxchg : MaskedAtomicRMWFiveArgIntrinsics;
} // TargetPrefix = "riscv"